U.S. Pat. No. 6,384,664 discloses a fuse circuit for detecting the resistor difference between a poly fuse under detection and a matching reference fuse, which are in two legs at a top of an electrical bridge circuit. Two more legs at a bottom of the electrical bridge circuit have matched transistors. When the fuse under detection is not burned, the differential voltage across the bridge circuit remains at zero. When the fuse is burned, a comparator detects a transition in differential voltage across the bridge circuit. The comparator has a flip flop latch that will trip and store the data. The differential voltage is impressed on an output of an inverter with a long decay pulse, which delays turn off of the differential voltage before the latch trips. Because of difficulty to predict the slope of the inverter decay voltage, the timing of the latch trip lacks control. No control logic exists that would control the timing. The fuse circuit is unable to adjust its sensitivity to detect the fuse resistance value.
U.S. Pat. No. 6,498,526 discloses a fuse circuit for detecting the resistor difference between a fuse under detection and a reference fuse, which are in an electrical bridge circuit that produces a differential output current proportional to the resistor difference. The system logic of an EPROM has an MRS1 register that provides a control signal pulse. A second MRS2 register of the EPROM provides a fuse program signal pulse. The fuse under detection can be programmed with a resistance value. The status of the value is indicated by the value of the differential output current. A disadvantage is that the control signals MRS1 and MRS2 operate by precisely timed steps; precharge, generate a voltage and place on a sensing circuit, and latch the detected value data. Such timing is difficult to control due to process variations that fabricate manufactured variations in semiconductor structures. A further disadvantage is that the fuse status value data is shifted to a register of the EPROM system logic. Manufactured variations in semiconductor structures alter the timing by the control signals MRS1 and MRS2, which causes rippling and corruption of the status values, while being shifted to a register as retained data.